One class of nonvolatile memory devices includes electrically erasable programmable read only memory (EEPROM), which may be used in many applications including embedded applications and mass storage applications. In typical embedded applications, an EEPROM device may be used to provide code storage in personal computers or mobile phones, for example, where fast random access read times may be required. Typical mass storage applications include memory card applications requiring high capacity and low cost.
One category of EEPROM devices includes NAND-type flash memories, which can provide a low cost and high capacity alternative to other forms of nonvolatile memory. FIG. 1A illustrates a conventional flash memory array 10 having a plurality of NAND-type strings therein. Each of these NAND-type strings includes a plurality of EEPROM cells, which are associated with respective even and odd bit lines (BL0—e, BL0—o, . . . , BLn_e, BLn_o). These bit lines are connected to a page buffer 12 having a plurality of buffer circuits (PB0, . . . , PBn) therein. Each EEPROM cell includes a floating gate electrode and a control gate electrode, which is electrically connected to a respective word line (WL0, WL1, . . . , WLn). Access to each NAND string is enabled by driving a string select line (SSL) to a logic 1 voltage during reading and programming operations. Each NAND string also includes a respective ground select transistor, which is electrically connected to a ground select line (GSL).
As illustrated by FIG. 1B, the EEPROM cells within the flash memory array 10 of FIG. 1A may be cells that support a single programmed state. EEPROM cells that support only a single programmed state are typically referred to as single level cells (SLC). In particular, an SLC may support an erased state, which may be treated as a logic 1 storage value, and a programmed state, which may be treated as a logic 0 storage value. The SLC may have a negative threshold voltage (Vth) when erased (e.g., −3V<Vth<−1V) and a positive threshold voltage when programmed (e.g., 1V<Vth<3V). This programmed state may be achieved by setting the bit line BL to a logic 0 value (e.g., 0 Volts), applying a program voltage (Vpgm) to a selected EEPROM cell and applying a pass voltage (Vpass) to the unselected EEPROM cells within a string, as illustrated by FIG. 1C. In addition, during programming the NAND string may be enabled by applying a positive voltage (e.g., power supply voltage Vdd) to the string select line (SSL) and a ground voltage (e.g., 0 Volts) to the ground select line (GSL).
Moreover, the programmed state or erased state of an EEPROM cell may be detected by performing a read operation on a selected cell. As illustrated by FIG. 1D, a NAND string will operate to discharge a precharged bit line BL when a selected cell is in an erased state and the selected word line voltage (e.g., 0 Volts) is greater than the threshold voltage of the selected cell. However, when a selected cell is in a programmed state, the corresponding NAND string will provide an open circuit to the precharged bit line BL because the selected word line voltage (e.g., 0 Volts) is less than the threshold voltage of the selected cell and the selected cell remains “off”. Other aspects of NAND-type flash memories are disclosed in an article by Jung et al., entitled “A 3.3 Volt Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. 1748-1757, November (1997), the disclosure of which is hereby incorporated herein by reference.
EEPROM cells that support multiple programmed states are typically referred to as multi-level cells (MLC). As illustrated by FIG. 2, an MLC that supports an erased state and three different programmed states operates to store two data bits per cell. These and other aspects of an MLC having two data bits per cell is disclosed in an article by Takeuchi et al., entitled “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228-1238, August (1998). Commonly assigned U.S. Pat. Nos. 5,862,074 and 5,768,188 also disclose aspects of multi-level EEPROM cells arranged in a NAND-type configuration, the disclosures of which are hereby incorporated herein by reference.
FIGS. 3A-3B illustrate how a pair of three-state EEPROM cells may support 3-bit programming. In FIG. 3A, an MLC is illustrated as supporting an erased state and two possible programmed states. As will be understood by those skilled in the art, the erased state may be distinguished from the two possible programmed states by applying a first reference voltage VR1 to a control electrode of a selected EEPROM cell during a read operation. This first reference voltage VR1 should be set to a level between the maximum acceptable threshold voltage of an erased cell (shown as V0) and the minimum acceptable threshold voltage of a cell programmed to state 1 (shown as V1). Similarly, the second programmed state (state 2) may be distinguished from the erased and first programmed states by applying a second reference voltage VR2 to a selected EEPROM cell during a read operation. This second reference voltage VR2 should be set to a level between the maximum acceptable threshold voltage of a cell programmed to state 1 and the minimum acceptable threshold voltage of a cell programmed to state 2 (shown as V2). As illustrated by FIG. 3B, two adjacent three-level EEPROM cells in the same physical row of memory may be programmed into one of eight possible states ((111), (110), . . . , (001), (000)) to support 3-bits of data per cell pair. Additional aspects of three-state EEPROM cells are disclosed in an article by Tanaka et al., entitled “A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Saving 40% Die Size Per Bit,” 1997 Symposium on VLSI Circuits Digest of Technical Papers, Section 9.3, pp. 65-66 (1997). Unfortunately, the use of 3-state EEPROM cells in the pair configuration of FIG. 3B may require the use of complex error detection and correction circuitry because any single cell failure will typically result in a corresponding 3-bit data error for both cells in the corresponding pair.